1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor memory device including a page buffer circuit.
2. Description of the Related Art
In general, semiconductor memory devices are classified into volatile memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), and nonvolatile memory devices, such as programmable read only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory. Unlikely volatile memory devices, nonvolatile memory devices retain data stored therein even without power, and thus nonvolatile memory devices do not require additional circuits for retaining stored data. For reference, volatile memory devices are superior to nonvolatile memory devices in terms of circuit size and access operation speed for a given storage capacity.
Flash memory devices, a representative nonvolatile memory device, stores data in memory cells through programming operations and erasing operations. Programming operations entail the accumulation of electrons in a floating gate of a transistor that forms a memory cell. In an erasing operation, electrons accumulated in the floating gate of the transistor are discharged to the substrate. Through such operations, flash memory devices store data corresponding to ‘1’ or ‘0’ in the memory cells. Furthermore, flash memory devices output stored data through sensing operations. A sensing operation detects the amount of negative charge (i.e. electrons) in the floating gate, and the flash memory device determines whether the stored data has a value of ‘1’ or ‘0’ using the sensing operation, and then outputs the stored data.
As described above, data (‘0’ or ‘1’) is stored in a single memory cell. When one bit data is stored in one memory cell, the memory cell is called a single level cell (SLC). When multi-bit data is stored in a single memory cell, these memory cells are called multi-level cells (MLC). In a single level cell, one determination voltage is required to determine the data stored in a memory cell, and in a multi-level cell, at least three determination voltages are required to determine the data stored in a memory cell. For example, three determination voltages are required to determine data having values of ‘00’, ‘01’, ‘10’, and ‘11’.
FIG. 1 is a diagram for explaining the threshold voltage distribution of memory cells of an MLC flash memory. Referring to FIG. 1, the threshold voltage distributions corresponding to a bi-level cell (BLC) scheme are formed through programming operations for storing data in the memory cells. Each of the threshold voltage distributions of the memory cells corresponds to data having values of ‘11’, ‘01’, ‘00’, and ‘10’.
In programming a BLC memory cell, which is capable of storing 2 bit data, a lower bit (i.e., a least significant bit, LSB) is programmed and then an upper bit (i.e., a most significant bit, MSB) is programmed. In the programming operation, an incremental step pulse programming (ISPP) scheme, in which a program voltage increases step by step, is generally used.